(1) Field of the Invention
The present invention relates to methods use to fabricate semiconductor devices, and more specifically to a method of forming shallow trench isolation (STI), regions, with improved comer rounding at the STI-semiconductor interface.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has resulted in the migration from LOCOS, (local oxidation of silicon), isolation technology to an STI isolation technology. Narrow active device regions, comprised with sub-micron features become difficult to maintain when isolation regions are formed via LOCOS technology. Birds beak formation, or encroachment of the silicon dioxide isolation region obtained via thermal oxidation procedures, into the adjacent silicon regions result in undesirable consumption of the designed active device region. The use of STI allows the design dimensions of the active device region to be maintained due to the absence of a thermal oxidation procedure used to grow a thick silicon dioxide isolation region. The STI regions are formed via definition of shallow trench shapes in a top portion of a semiconductor substrate, followed by insulator filling and planarization procedures.
The STI technology while not consuming adjacent silicon of an active device region, however presents other unwanted phenomena, again at the isolation region-semiconductor interface. The dry etch procedures used to define the shallow trench shapes in a top portion of the semiconductor substrate, create a sharp corner in the active device region at the STI-semiconductor interface. The sharp corner can result in an unwanted high electric field region for the active device region, translating to deleterious device parameters such as sub-threshold leakage.
This invention will describe a novel process sequence for fabrication of STI regions, in which corner rounding of adjacent active device regions is reduced. This is accomplished via use of a combination of process steps, such as formation and removal of a thin LOCOS region, and insulator spacer formation performed prior to definition of the shallow trench shapes. Prior art, such as Gambino et al, in U.S. Pat. No. 6,084,276, Reinberg, in U.S. Pat. No. 6,265,281 B1, Jang et al, in U.S. Pat. No. 6,037,018, and Lin et al, in U.S. Pat. No. 6,207,532 B1, describe methods of forming STI regions as well as methods addressing corner rounding. None of these prior art however describe the novel process sequence used in the present invention, in which a combination of steps such as thin LOCOS formation and removal and formation of sidewall spacers, are employed prior to definition of the shallow trench shapes.
It is an object of this invention to form STI regions in a top portion of a semiconductor substrate, wherein the STI regions are located adjacent to active device regions which feature rounded comers at the active device regionxe2x80x94STI interface.
It is another object of this invention to form and then remove, a thin, LOCOS region from a top surface of a first region of semiconductor to be used to accommodate an STI region, resulting in rounded corners for an adjacent, second region of semiconductor to be used for an active device region.
It is still another object of the invention to form insulator spacers on the sides of an insulator shape overlying the active device region, with the insulator spacers overlying a portion of the rounded corners of the active device region.
It is still yet another object of this invention to define the shallow trench shapes in a top portion of the first region of semiconductor, in an area in which the first region of semiconductor is not covered by the insulator spacers.
In accordance with the present invention a method of forming an STI region in a top portion of a semiconductor substrate, in which corner rounding of the portion of active device region located adjacent to the STI region is obtained, is described. After formation of an opening in a oxidation resistant material exposing a first region of semiconductor, an ion implantation procedure is performed to prepare the first region of semiconductor for an oxidation procedure. Formation of a thin LOCOS region in the implanted, first region of semiconductor is followed by removal of the thin LOCOS region, resulting in a recessed first region of semiconductor featuring rounded corners in an adjacently located second region of semiconductor, the subsequent active device region now underlying the oxidation resistant shape. Insulator spacers are formed on the sides of the oxidation resistant shape, overlying the rounded corners of the recessed, first region or semiconductor. Definition of a shallow trench shape is next accomplished in the portion of the recessed, first region of semiconductor, not covered by the insulator spacers. After thermal growth of an insulator liner layer on the exposed surfaces of the shallow trench shape, additional insulator layer is deposited completely filling the shallow trench opening. Selective removal of unwanted portions of the deposited insulator layer from the top surface of the oxidation resistant shape, results in an STI region located adjacent to an active device region, wherein the active device region in turn features rounded corners overlaid by insulator spacers.